Autostart PD-2.7 Podręcznik Użytkownika
Przeglądaj online lub pobierz Podręcznik Użytkownika dla Zdalne rozruszniki Autostart PD-2.7. Autostart PD-2.7 User guide Instrukcja obsługi
- Strona / 170
- Spis treści
- BOOKMARKI
- Spartan-6 FPGA 1
- Configuration 1
- Revision History 3
- Table of Contents 7
- Chapter 4: User Primitives 8
- Chapter 8: Readback CRC 10
- About This Guide 13
- Additional Resources 14
- Configuration Overview 15
- Design Considerations 16
- Slave Modes 17
- UG380_c1_02_051109 18
- Serial SelectMAP 18
- MultiBoot /Safe Update 20
- Required I/O Voltages 20
- Nonvolatile Data Storage 20
- FPGA Density Migration 21
- Production Lifetime 21
- Configuration Factors 22
- Chapter 2 23
- Master Serial 26
- Slave Serial Configuration 27
- Spartan-6 28
- Microprocessor 28
- Platform Flash 32
- SelectMAP Data Loading 35
- SelectMAP Data Ordering 39
- SPI Configuration Interface 40
- SPI Flash 42
- W25Q SPI 43
- UG380_c2_14_011310 44
- Master SPI Timing Waveform 45
- Power-On Sequence Precautions 46
- SPI Serial Daisy-Chain 47
- Chapter 3 59
- Data Valid 60
- User Primitives 65
- ICAP_SPARTAN6 66
- STARTUP_SPARTAN6 67
- SUSPEND_SYNC 68
- POST_CRC_INTERNAL 69
- Chapter 4: User Primitives 70
- Configuration Details 71
- Pin Name Type 72
- Description 72
- Bitstream Overview 75
- Generating PROM Files 77
- UG380_c5_01_042909 78
- Parallel Bus Bit Order 79
- Configuration Sequence 80
- Setup (Steps 1-3) 81
- UG380_c5_04_050812 82
- Sample Mode Pins (Step 3) 83
- UG380_c5_05_042909 83
- UG380_c5_06_042909 83
- Synchronization (Step 4) 84
- Check Device ID (Step 5) 84
- UG380_c5_07_042909 84
- UG380_c5_08_042909 84
- Startup (Step 8) 86
- Phase Event 87
- Signal Name Type Access 88
- Bitstream Encryption 89
- Loading the Encryption Key 90
- Loading Encrypted Bitstreams 90
- Configuration Memory Frames 95
- Type 1 Packet 96
- Type 2 Packet 96
- Configuration Registers 97
- CRC Register 98
- CBC_REG Register 100
- IDCODE Register 100
- CSBO Register 100
- Command Register (CMD) 100
- Control Register 0 (CTL) 101
- Status Register (STAT) 102
- Configuration Packets 103
- Suspend Register (PWRDN_REG) 104
- Frame Length Register 104
- Multi-Frame Write Register 104
- HC_OPT_REG Register 105
- MODE Register 106
- CCLK_FREQ Register 107
- PU_GWE Register 107
- PU_GTS Register 107
- SEU_OPT Register 108
- DNA_PORT 109
- UG380_c5_14_052009 110
- Read = 0 110
- X = Don’t care 110
- ↑ = Rising clock edge 110
- UG380_c5_15_121112 111
- UG380_c5_16_021010 111
- UG380_c5_17_052009 112
- UG380 (v2.7) October 29, 2014 113
- Readback and Configuration 115
- Verification 115
- Readback Command Sequences 116
- AA 99 55 66 28 00 E0 0 0 117
- Verifying Readback Data 127
- UG380_c6_04_042909 128
- MSK and BIT Files 129
- Reconfiguration and MultiBoot 131
- Fallback MultiBoot 132
- IPROG Reconfiguration 134
- Watchdog Timer 135
- Readback CRC 137
- CRC Masking 138
- Chapter 8: Readback CRC 140
- Distributed RAM 141
- Post_CRC Constraints 142
- POST_CRC 143
- POST_CRC_INIT_FLAG 143
- POST_CRC_SOURCE 143
- POST_CRC_ACTION 144
- POST_CRC_FREQ 144
- Chapter 9 145
- Mixed Serial Daisy-Chains 146
- Startup Sequencing (GTS) 147
- Active DONE Driver 147
- Connect All DONE Pins 147
- DONE Pin Rise Time 147
- Bitstream Formatting 147
- Parallel Daisy-Chain 151
- Ganged SelectMAP 152
- UG380_c9_06_021710 153
- ABORT Status Word 154
- SelectMAP Reconfiguration 155
- Advanced JTAG Configurations 157
- JTAG Configuration/Readback 158
- Boundary-Scan Register 161
- Instruction Register 162
- UG380_c10_03_102014 162
- BYPASS Register 164
- JTAG Configuration Register 164
- USERCODE Register 164
- Load CFG_IN 166
- Instruction 166
- Single Device Configuration 167
- Multiple Device Configuration 168
Podsumowanie treści
Spartan-6 FPGA ConfigurationUser GuideUG380 (v2.7) October 29, 2014
10 www.xilinx.com Spartan-6 FPGA Configuration User GuideUG380 (v2.7) October 29, 2014PU_GWE Register. . . . . . . . . . . . . . . . . . . . . . . . .
100 www.xilinx.com Spartan-6 FPGA Configuration User GuideUG380 (v2.7) October 29, 2014Chapter 5: Configuration DetailsCBC_REG RegisterThis register i
Spartan-6 FPGA Configuration User Guide www.xilinx.com 101UG380 (v2.7) October 29, 2014Configuration PacketsControl Register 0 (CTL)The CTL register i
102 www.xilinx.com Spartan-6 FPGA Configuration User GuideUG380 (v2.7) October 29, 2014Chapter 5: Configuration DetailsCaution! PERSIST and ICAP canno
Spartan-6 FPGA Configuration User Guide www.xilinx.com 103UG380 (v2.7) October 29, 2014Configuration PacketsConfiguration Options Register (COR1 and C
104 www.xilinx.com Spartan-6 FPGA Configuration User GuideUG380 (v2.7) October 29, 2014Chapter 5: Configuration DetailsSuspend Register (PWRDN_REG)Fra
Spartan-6 FPGA Configuration User Guide www.xilinx.com 105UG380 (v2.7) October 29, 2014Configuration PacketsConfiguration Watchdog Timer RegisterThe c
106 www.xilinx.com Spartan-6 FPGA Configuration User GuideUG380 (v2.7) October 29, 2014Chapter 5: Configuration DetailsIf it is a known-vendor command
Spartan-6 FPGA Configuration User Guide www.xilinx.com 107UG380 (v2.7) October 29, 2014Configuration PacketsCCLK_FREQ RegisterPU_GWE RegisterThis 10-b
108 www.xilinx.com Spartan-6 FPGA Configuration User GuideUG380 (v2.7) October 29, 2014Chapter 5: Configuration DetailsSEU_OPT RegisterThis register e
Spartan-6 FPGA Configuration User Guide www.xilinx.com 109UG380 (v2.7) October 29, 2014Default Initial Configuration ProcessDefault Initial Configurat
Spartan-6 FPGA Configuration User Guide www.xilinx.com 11UG380 (v2.7) October 29, 2014POST_CRC_FREQ . . . . . . . . . . . . . . . . . . . . . . . . .
110 www.xilinx.com Spartan-6 FPGA Configuration User GuideUG380 (v2.7) October 29, 2014Chapter 5: Configuration DetailsIdentifier ValueAs shown in Fig
Spartan-6 FPGA Configuration User Guide www.xilinx.com 111UG380 (v2.7) October 29, 2014Spartan-6 FPGA Unique Device Identifier (Device DNA)Identifier
112 www.xilinx.com Spartan-6 FPGA Configuration User GuideUG380 (v2.7) October 29, 2014Chapter 5: Configuration DetailsIt is also possible to add addi
Spartan-6 FPGA Configuration User Guide www.xilinx.com 113UG380 (v2.7) October 29, 2014Bitstream Compressionhave the greatest overall compression fact
114 www.xilinx.com Spartan-6 FPGA Configuration User GuideUG380 (v2.7) October 29, 2014Chapter 5: Configuration Details
Spartan-6 FPGA Configuration User Guide www.xilinx.com 115UG380 (v2.7) October 29, 2014Chapter 6Readback and Configuration VerificationSpartan®-6 devi
116 www.xilinx.com Spartan-6 FPGA Configuration User GuideUG380 (v2.7) October 29, 2014Chapter 6: Readback and Configuration VerificationReadback Comm
Spartan-6 FPGA Configuration User Guide www.xilinx.com 117UG380 (v2.7) October 29, 2014Readback Command Sequences2. Write the read STAT register packe
118 www.xilinx.com Spartan-6 FPGA Configuration User GuideUG380 (v2.7) October 29, 2014Chapter 6: Readback and Configuration VerificationTo read regis
Spartan-6 FPGA Configuration User Guide www.xilinx.com 119UG380 (v2.7) October 29, 2014Readback Command SequencesTable 6-2 shows the readback command
12 www.xilinx.com Spartan-6 FPGA Configuration User GuideUG380 (v2.7) October 29, 2014
120 www.xilinx.com Spartan-6 FPGA Configuration User GuideUG380 (v2.7) October 29, 2014Chapter 6: Readback and Configuration VerificationUser logic sh
Spartan-6 FPGA Configuration User Guide www.xilinx.com 121UG380 (v2.7) October 29, 2014Readback Command SequencesConfiguration Register Read Procedure
122 www.xilinx.com Spartan-6 FPGA Configuration User GuideUG380 (v2.7) October 29, 2014Chapter 6: Readback and Configuration VerificationThe packets s
Spartan-6 FPGA Configuration User Guide www.xilinx.com 123UG380 (v2.7) October 29, 2014Readback Command SequencesConfiguration Memory Read Procedure (
124 www.xilinx.com Spartan-6 FPGA Configuration User GuideUG380 (v2.7) October 29, 2014Chapter 6: Readback and Configuration VerificationTable 6-6: Sh
Spartan-6 FPGA Configuration User Guide www.xilinx.com 125UG380 (v2.7) October 29, 2014Readback Command Sequences7Shift configuration packets into the
126 www.xilinx.com Spartan-6 FPGA Configuration User GuideUG380 (v2.7) October 29, 2014Chapter 6: Readback and Configuration VerificationTable 6-7 lis
Spartan-6 FPGA Configuration User Guide www.xilinx.com 127UG380 (v2.7) October 29, 2014Verifying Readback DataVerifying Readback DataThe readback data
128 www.xilinx.com Spartan-6 FPGA Configuration User GuideUG380 (v2.7) October 29, 2014Chapter 6: Readback and Configuration VerificationThe drawback
Spartan-6 FPGA Configuration User Guide www.xilinx.com 129UG380 (v2.7) October 29, 2014Verifying Readback DataThe RBA and RBB files contain expected r
Spartan-6 FPGA Configuration User Guide www.xilinx.com 13UG380 (v2.7) October 29, 2014PrefaceAbout This GuideThis document describes Spartan®-6 FPGA c
130 www.xilinx.com Spartan-6 FPGA Configuration User GuideUG380 (v2.7) October 29, 2014Chapter 6: Readback and Configuration Verification
Spartan-6 FPGA Configuration User Guide www.xilinx.com 131UG380 (v2.7) October 29, 2014Chapter 7Reconfiguration and MultiBootMultiBoot OverviewBecause
132 www.xilinx.com Spartan-6 FPGA Configuration User GuideUG380 (v2.7) October 29, 2014Chapter 7: Reconfiguration and MultiBootFallback MultiBootFallb
Spartan-6 FPGA Configuration User Guide www.xilinx.com 133UG380 (v2.7) October 29, 2014Fallback MultiBootThere are three images for MultiBoot configur
134 www.xilinx.com Spartan-6 FPGA Configuration User GuideUG380 (v2.7) October 29, 2014Chapter 7: Reconfiguration and MultiBootIPROG ReconfigurationTh
Spartan-6 FPGA Configuration User Guide www.xilinx.com 135UG380 (v2.7) October 29, 2014Status Register for Fallback and IPROG ReconfigurationAfter the
136 www.xilinx.com Spartan-6 FPGA Configuration User GuideUG380 (v2.7) October 29, 2014Chapter 7: Reconfiguration and MultiBootregister or setting the
Spartan-6 FPGA Configuration User Guide www.xilinx.com 137UG380 (v2.7) October 29, 2014Chapter 8Readback CRCSpartan®-6 devices include a feature to pe
138 www.xilinx.com Spartan-6 FPGA Configuration User GuideUG380 (v2.7) October 29, 2014Chapter 8: Readback CRC• In addition, the JTAG instruction regi
Spartan-6 FPGA Configuration User Guide www.xilinx.com 139UG380 (v2.7) October 29, 2014CRC MaskingThere are two types of CLBs, those containing SLICEM
14 www.xilinx.com Spartan-6 FPGA Configuration User GuideUG380 (v2.7) October 29, 2014Preface: About This Guide•Spartan-6 FPGA Clocking Resources User
140 www.xilinx.com Spartan-6 FPGA Configuration User GuideUG380 (v2.7) October 29, 2014Chapter 8: Readback CRCCLBs Near Top or Bottom IOI Using DRPUsi
Spartan-6 FPGA Configuration User Guide www.xilinx.com 141UG380 (v2.7) October 29, 2014CRC MaskingCLBs Near Top or Bottom IOI DRP with LUTs Configured
142 www.xilinx.com Spartan-6 FPGA Configuration User GuideUG380 (v2.7) October 29, 2014Chapter 8: Readback CRCBecause JTAG has the highest priority in
Spartan-6 FPGA Configuration User Guide www.xilinx.com 143UG380 (v2.7) October 29, 2014Post_CRC Constraints• PRE_COMPUTEDBitGen calculates the CRC val
144 www.xilinx.com Spartan-6 FPGA Configuration User GuideUG380 (v2.7) October 29, 2014Chapter 8: Readback CRCPOST_CRC_ACTIONUCF Syntax ExampleCONFIG
Spartan-6 FPGA Configuration User Guide www.xilinx.com 145UG380 (v2.7) October 29, 2014Chapter 9Advanced Configuration InterfacesSerial Daisy-ChainsMu
146 www.xilinx.com Spartan-6 FPGA Configuration User GuideUG380 (v2.7) October 29, 2014Chapter 9: Advanced Configuration Interfaces3. The BitGen start
Spartan-6 FPGA Configuration User Guide www.xilinx.com 147UG380 (v2.7) October 29, 2014Ganged Serial ConfigurationGuidelines and Design Considerations
148 www.xilinx.com Spartan-6 FPGA Configuration User GuideUG380 (v2.7) October 29, 2014Chapter 9: Advanced Configuration Interfacestypically set for M
Spartan-6 FPGA Configuration User Guide www.xilinx.com 149UG380 (v2.7) October 29, 2014Multiple Device SelectMAP Configuration9. Ganged serial configu
Spartan-6 FPGA Configuration User Guide www.xilinx.com 15UG380 (v2.7) October 29, 2014Chapter 1Configuration OverviewOverviewSpartan®-6 FPGAs are conf
150 www.xilinx.com Spartan-6 FPGA Configuration User GuideUG380 (v2.7) October 29, 2014Chapter 9: Advanced Configuration InterfacesIf Readback is goin
Spartan-6 FPGA Configuration User Guide www.xilinx.com 151UG380 (v2.7) October 29, 2014Parallel Daisy-ChainParallel Daisy-ChainSpartan-6 FPGA configur
152 www.xilinx.com Spartan-6 FPGA Configuration User GuideUG380 (v2.7) October 29, 2014Chapter 9: Advanced Configuration InterfacesGanged SelectMAPIt
Spartan-6 FPGA Configuration User Guide www.xilinx.com 153UG380 (v2.7) October 29, 2014SelectMAP ABORT7. The Xilinx PROM must be set for parallel mode
154 www.xilinx.com Spartan-6 FPGA Configuration User GuideUG380 (v2.7) October 29, 2014Chapter 9: Advanced Configuration InterfacesReadback Abort Sequ
Spartan-6 FPGA Configuration User Guide www.xilinx.com 155UG380 (v2.7) October 29, 2014SelectMAP ReconfigurationThe ABORT sequence lasts four CCLK cyc
156 www.xilinx.com Spartan-6 FPGA Configuration User GuideUG380 (v2.7) October 29, 2014Chapter 9: Advanced Configuration Interfaces
Spartan-6 FPGA Configuration User Guide www.xilinx.com 157UG380 (v2.7) October 29, 2014Chapter 10Advanced JTAG ConfigurationsIntroductionSpartan®-6 de
158 www.xilinx.com Spartan-6 FPGA Configuration User GuideUG380 (v2.7) October 29, 2014Chapter 10: Advanced JTAG ConfigurationsJTAG Configuration/Read
Spartan-6 FPGA Configuration User Guide www.xilinx.com 159UG380 (v2.7) October 29, 2014JTAG Configuration/ReadbackThe operation of each state is descr
16 www.xilinx.com Spartan-6 FPGA Configuration User GuideUG380 (v2.7) October 29, 2014Chapter 1: Configuration Overviewof UG628, Command Line Tools Us
160 www.xilinx.com Spartan-6 FPGA Configuration User GuideUG380 (v2.7) October 29, 2014Chapter 10: Advanced JTAG ConfigurationsSpartan-6 devices suppo
Spartan-6 FPGA Configuration User Guide www.xilinx.com 161UG380 (v2.7) October 29, 2014JTAG Configuration/Readback3. Overwrite the FPGA configuration
162 www.xilinx.com Spartan-6 FPGA Configuration User GuideUG380 (v2.7) October 29, 2014Chapter 10: Advanced JTAG ConfigurationsInternal pull-up and pu
Spartan-6 FPGA Configuration User Guide www.xilinx.com 163UG380 (v2.7) October 29, 2014JTAG Configuration/ReadbackTo invoke an operation, the desired
164 www.xilinx.com Spartan-6 FPGA Configuration User GuideUG380 (v2.7) October 29, 2014Chapter 10: Advanced JTAG ConfigurationsTable 10-3 shows the in
Spartan-6 FPGA Configuration User Guide www.xilinx.com 165UG380 (v2.7) October 29, 2014JTAG Configuration/ReadbackUsing Boundary-Scan in Spartan-6 Dev
166 www.xilinx.com Spartan-6 FPGA Configuration User GuideUG380 (v2.7) October 29, 2014Chapter 10: Advanced JTAG ConfigurationsX-Ref Target - Figure 1
Spartan-6 FPGA Configuration User Guide www.xilinx.com 167UG380 (v2.7) October 29, 2014JTAG Configuration/ReadbackSingle Device ConfigurationTable 10-
168 www.xilinx.com Spartan-6 FPGA Configuration User GuideUG380 (v2.7) October 29, 2014Chapter 10: Advanced JTAG ConfigurationsMultiple Device Configu
Spartan-6 FPGA Configuration User Guide www.xilinx.com 169UG380 (v2.7) October 29, 2014JTAG Configuration/ReadbackWhen the shutdown sequence is clocke
Spartan-6 FPGA Configuration User Guide www.xilinx.com 17UG380 (v2.7) October 29, 2014Design ConsiderationsSlave ModesThe externally controlled loadin
170 www.xilinx.com Spartan-6 FPGA Configuration User GuideUG380 (v2.7) October 29, 2014Chapter 10: Advanced JTAG Configurations
18 www.xilinx.com Spartan-6 FPGA Configuration User GuideUG380 (v2.7) October 29, 2014Chapter 1: Configuration OverviewThe Slave SelectMAP mode is a s
Spartan-6 FPGA Configuration User Guide www.xilinx.com 19UG380 (v2.7) October 29, 2014Design ConsiderationsThe Low-Cost Priority SolutionThe option wi
Spartan-6 FPGA Configuration User Guide www.xilinx.com UG380 (v2.7) October 29, 2014Notice of DisclaimerThe information disclosed to you hereunder (th
20 www.xilinx.com Spartan-6 FPGA Configuration User GuideUG380 (v2.7) October 29, 2014Chapter 1: Configuration Overviewand broad interoperability. It
Spartan-6 FPGA Configuration User Guide www.xilinx.com 21UG380 (v2.7) October 29, 2014Design ConsiderationsFPGA Density MigrationThe package footprint
22 www.xilinx.com Spartan-6 FPGA Configuration User GuideUG380 (v2.7) October 29, 2014Chapter 1: Configuration OverviewLoading Multiple FPGAs with the
Spartan-6 FPGA Configuration User Guide www.xilinx.com 23UG380 (v2.7) October 29, 2014Chapter 2Configuration Interface BasicsThis chapter provides qui
24 www.xilinx.com Spartan-6 FPGA Configuration User GuideUG380 (v2.7) October 29, 2014Chapter 2: Configuration Interface BasicsSerial Configuration In
Spartan-6 FPGA Configuration User Guide www.xilinx.com 25UG380 (v2.7) October 29, 2014Serial Configuration InterfaceTable 2-2 describes the serial con
26 www.xilinx.com Spartan-6 FPGA Configuration User GuideUG380 (v2.7) October 29, 2014Chapter 2: Configuration Interface BasicsMaster SerialThe Master
Spartan-6 FPGA Configuration User Guide www.xilinx.com 27UG380 (v2.7) October 29, 2014Serial Configuration Interface5. The Spartan-6 FPGA VCCO_2 suppl
28 www.xilinx.com Spartan-6 FPGA Configuration User GuideUG380 (v2.7) October 29, 2014Chapter 2: Configuration Interface BasicsNotes relevant to Figur
Spartan-6 FPGA Configuration User Guide www.xilinx.com 29UG380 (v2.7) October 29, 2014Serial Configuration Interface3. The CCLK net requires Thevenin
UG380 (v2.7) October 29, 2014 www.xilinx.com Spartan-6 FPGA Configuration User GuideRevision HistoryThe following table shows the revision history for
30 www.xilinx.com Spartan-6 FPGA Configuration User GuideUG380 (v2.7) October 29, 2014Chapter 2: Configuration Interface BasicsSelectMAP Configuration
Spartan-6 FPGA Configuration User Guide www.xilinx.com 31UG380 (v2.7) October 29, 2014SelectMAP Configuration InterfaceTable 2-3 describes the SelectM
32 www.xilinx.com Spartan-6 FPGA Configuration User GuideUG380 (v2.7) October 29, 2014Chapter 2: Configuration Interface BasicsPlatform Flash PROM Sel
Spartan-6 FPGA Configuration User Guide www.xilinx.com 33UG380 (v2.7) October 29, 2014SelectMAP Configuration Interface2. The CCLK net requires Theven
34 www.xilinx.com Spartan-6 FPGA Configuration User GuideUG380 (v2.7) October 29, 2014Chapter 2: Configuration Interface BasicsMicroprocessor-Driven S
Spartan-6 FPGA Configuration User Guide www.xilinx.com 35UG380 (v2.7) October 29, 2014SelectMAP Configuration Interface3. For more details on CCLK ter
36 www.xilinx.com Spartan-6 FPGA Configuration User GuideUG380 (v2.7) October 29, 2014Chapter 2: Configuration Interface BasicsRDWR_BRDWR_B is an inpu
Spartan-6 FPGA Configuration User Guide www.xilinx.com 37UG380 (v2.7) October 29, 2014SelectMAP Configuration InterfaceNotes relevant to Figure 2-8:1.
38 www.xilinx.com Spartan-6 FPGA Configuration User GuideUG380 (v2.7) October 29, 2014Chapter 2: Configuration Interface BasicsNotes relevant to Figur
Spartan-6 FPGA Configuration User Guide www.xilinx.com 39UG380 (v2.7) October 29, 2014SelectMAP Configuration InterfaceNotes relevant to Figure 2-10:1
Spartan-6 FPGA Configuration User Guide www.xilinx.com UG380 (v2.7) October 29, 201402/22/2010 2.1 Changed the supported encryption data widths to x1
40 www.xilinx.com Spartan-6 FPGA Configuration User GuideUG380 (v2.7) October 29, 2014Chapter 2: Configuration Interface BasicsSPI Configuration Inter
Spartan-6 FPGA Configuration User Guide www.xilinx.com 41UG380 (v2.7) October 29, 2014SPI Configuration InterfaceDIN/D0/MISO/MISO[1]Input Master FPGA
42 www.xilinx.com Spartan-6 FPGA Configuration User GuideUG380 (v2.7) October 29, 2014Chapter 2: Configuration Interface BasicsNotes relevant to Figur
Spartan-6 FPGA Configuration User Guide www.xilinx.com 43UG380 (v2.7) October 29, 2014SPI Configuration Interface8. There are additional pins on the S
44 www.xilinx.com Spartan-6 FPGA Configuration User GuideUG380 (v2.7) October 29, 2014Chapter 2: Configuration Interface Basicscomplete list, see the
Spartan-6 FPGA Configuration User Guide www.xilinx.com 45UG380 (v2.7) October 29, 2014SPI Configuration InterfaceMaster SPI Timing WaveformFigure 2-15
46 www.xilinx.com Spartan-6 FPGA Configuration User GuideUG380 (v2.7) October 29, 2014Chapter 2: Configuration Interface BasicsIn x4 mode, the Fast-Re
Spartan-6 FPGA Configuration User Guide www.xilinx.com 47UG380 (v2.7) October 29, 2014Master BPI Configuration Interfaceconfiguration procedure such t
48 www.xilinx.com Spartan-6 FPGA Configuration User GuideUG380 (v2.7) October 29, 2014Chapter 2: Configuration Interface Basicsthrough the Spartan-6 d
Spartan-6 FPGA Configuration User Guide www.xilinx.com 49UG380 (v2.7) October 29, 2014Master BPI Configuration InterfaceDONE Bidirectional, Open-Drain
UG380 (v2.7) October 29, 2014 www.xilinx.com Spartan-6 FPGA Configuration User Guide06/27/2012 2.4 Updated bullet about VBATT being tied to VCCAUX or
50 www.xilinx.com Spartan-6 FPGA Configuration User GuideUG380 (v2.7) October 29, 2014Chapter 2: Configuration Interface BasicsNotes relevant to Figur
Spartan-6 FPGA Configuration User Guide www.xilinx.com 51UG380 (v2.7) October 29, 2014Master BPI Configuration Interface6. A24 and A25 can be in I/O b
52 www.xilinx.com Spartan-6 FPGA Configuration User GuideUG380 (v2.7) October 29, 2014Chapter 2: Configuration Interface BasicsFigure 2-21 shows the B
Spartan-6 FPGA Configuration User Guide www.xilinx.com 53UG380 (v2.7) October 29, 2014Master BPI Configuration InterfaceDetermining the Maximum Config
54 www.xilinx.com Spartan-6 FPGA Configuration User GuideUG380 (v2.7) October 29, 2014Chapter 2: Configuration Interface Basics• Hold the FPGA PROGRAM
Spartan-6 FPGA Configuration User Guide www.xilinx.com 55UG380 (v2.7) October 29, 2014Board Layout for Configuration Clock (CCLK)• Terminate the end o
56 www.xilinx.com Spartan-6 FPGA Configuration User GuideUG380 (v2.7) October 29, 2014Chapter 2: Configuration Interface BasicsFigure 2-23 shows the b
Spartan-6 FPGA Configuration User Guide www.xilinx.com 57UG380 (v2.7) October 29, 2014Board Layout for Configuration Clock (CCLK)Figure 2-25 shows a s
58 www.xilinx.com Spartan-6 FPGA Configuration User GuideUG380 (v2.7) October 29, 2014Chapter 2: Configuration Interface Basics
Spartan-6 FPGA Configuration User Guide www.xilinx.com 59UG380 (v2.7) October 29, 2014Chapter 3Boundary-Scan and JTAG ConfigurationIntroductionSpartan
Spartan-6 FPGA Configuration User Guide www.xilinx.com UG380 (v2.7) October 29, 2014
60 www.xilinx.com Spartan-6 FPGA Configuration User GuideUG380 (v2.7) October 29, 2014Chapter 3: Boundary-Scan and JTAG ConfigurationThe four mandator
Spartan-6 FPGA Configuration User Guide www.xilinx.com 61UG380 (v2.7) October 29, 2014Boundary-Scan for Spartan-6 Devices Using IEEE Std 1149.1Using B
62 www.xilinx.com Spartan-6 FPGA Configuration User GuideUG380 (v2.7) October 29, 2014Chapter 3: Boundary-Scan and JTAG ConfigurationThe devices in th
Spartan-6 FPGA Configuration User Guide www.xilinx.com 63UG380 (v2.7) October 29, 2014Design ConsiderationsConfiguring through Boundary-ScanIf the Spa
64 www.xilinx.com Spartan-6 FPGA Configuration User GuideUG380 (v2.7) October 29, 2014Chapter 3: Boundary-Scan and JTAG Configuration
Spartan-6 FPGA Configuration User Guide www.xilinx.com 65UG380 (v2.7) October 29, 2014Chapter 4User PrimitivesThe configuration primitives described i
66 www.xilinx.com Spartan-6 FPGA Configuration User GuideUG380 (v2.7) October 29, 2014Chapter 4: User PrimitivesICAP_SPARTAN6The ICAP_SPARTAN6 primiti
Spartan-6 FPGA Configuration User Guide www.xilinx.com 67UG380 (v2.7) October 29, 2014STARTUP_SPARTAN6STARTUP_SPARTAN6The STARTUP_SPARTAN6 primitive p
68 www.xilinx.com Spartan-6 FPGA Configuration User GuideUG380 (v2.7) October 29, 2014Chapter 4: User Primitivesrollover is desired, the DOUT port can
Spartan-6 FPGA Configuration User Guide www.xilinx.com 69UG380 (v2.7) October 29, 2014POST_CRC_INTERNALPOST_CRC_INTERNALPOST_CRC_INTERNAL provides fab
Spartan-6 FPGA Configuration User Guide www.xilinx.com 7UG380 (v2.7) October 29, 2014Revision History . . . . . . . . . . . . . . . . . . . . . . . .
70 www.xilinx.com Spartan-6 FPGA Configuration User GuideUG380 (v2.7) October 29, 2014Chapter 4: User Primitives
Spartan-6 FPGA Configuration User Guide www.xilinx.com 71UG380 (v2.7) October 29, 2014Chapter 5Configuration DetailsConfiguration PinsCertain pins are
72 www.xilinx.com Spartan-6 FPGA Configuration User GuideUG380 (v2.7) October 29, 2014Chapter 5: Configuration DetailsFPGA I/O Pin Settings During Con
Spartan-6 FPGA Configuration User Guide www.xilinx.com 73UG380 (v2.7) October 29, 2014Configuration PinsFloating signal levels are problematic in CMOS
74 www.xilinx.com Spartan-6 FPGA Configuration User GuideUG380 (v2.7) October 29, 2014Chapter 5: Configuration DetailsD2/MISO3 2 Persist No NoD[15:3]
Spartan-6 FPGA Configuration User Guide www.xilinx.com 75UG380 (v2.7) October 29, 2014Configuration Data File FormatsConfiguration Data File FormatsXi
76 www.xilinx.com Spartan-6 FPGA Configuration User GuideUG380 (v2.7) October 29, 2014Chapter 5: Configuration DetailsA Spartan-6 FPGA bitstream consi
Spartan-6 FPGA Configuration User Guide www.xilinx.com 77UG380 (v2.7) October 29, 2014Generating PROM Filesin x16 mode. The FPGA now knows on which bu
78 www.xilinx.com Spartan-6 FPGA Configuration User GuideUG380 (v2.7) October 29, 2014Chapter 5: Configuration DetailsBit SwappingBit swapping is the
Spartan-6 FPGA Configuration User Guide www.xilinx.com 79UG380 (v2.7) October 29, 2014Generating PROM FilesParallel Bus Bit OrderTraditionally, in Sel
8 www.xilinx.com Spartan-6 FPGA Configuration User GuideUG380 (v2.7) October 29, 2014SelectMAP Data Ordering . . . . . . . . . . . . . . . . . . . .
80 www.xilinx.com Spartan-6 FPGA Configuration User GuideUG380 (v2.7) October 29, 2014Chapter 5: Configuration DetailsDelaying ConfigurationThere are
Spartan-6 FPGA Configuration User Guide www.xilinx.com 81UG380 (v2.7) October 29, 2014Configuration SequenceSetup (Steps 1-3)The setup process is simi
82 www.xilinx.com Spartan-6 FPGA Configuration User GuideUG380 (v2.7) October 29, 2014Chapter 5: Configuration DetailsFigure 5-4 shows the power-up wa
Spartan-6 FPGA Configuration User Guide www.xilinx.com 83UG380 (v2.7) October 29, 2014Configuration Sequence2. TICCK is either TSPIICCK or TBPIICCK de
84 www.xilinx.com Spartan-6 FPGA Configuration User GuideUG380 (v2.7) October 29, 2014Chapter 5: Configuration DetailsBitstream Loading (Steps 4-7)The
Spartan-6 FPGA Configuration User Guide www.xilinx.com 85UG380 (v2.7) October 29, 2014Configuration SequenceThe Spartan-6 FPGA JTAG IDCODE register ha
86 www.xilinx.com Spartan-6 FPGA Configuration User GuideUG380 (v2.7) October 29, 2014Chapter 5: Configuration DetailsLoad Configuration Data Frames (
Spartan-6 FPGA Configuration User Guide www.xilinx.com 87UG380 (v2.7) October 29, 2014Configuration SequenceAfter the configuration frames are loaded,
88 www.xilinx.com Spartan-6 FPGA Configuration User GuideUG380 (v2.7) October 29, 2014Chapter 5: Configuration Details In a Slave configuration mode,
Spartan-6 FPGA Configuration User Guide www.xilinx.com 89UG380 (v2.7) October 29, 2014Bitstream EncryptionBitstream EncryptionThe Spartan-6 6SLX75/T,
Spartan-6 FPGA Configuration User Guide www.xilinx.com 9UG380 (v2.7) October 29, 2014Setup (Steps 1-3) . . . . . . . . . . . . . . . . . . . . . . . .
90 www.xilinx.com Spartan-6 FPGA Configuration User GuideUG380 (v2.7) October 29, 2014Chapter 5: Configuration DetailsLoading the Encryption KeyThe en
Spartan-6 FPGA Configuration User Guide www.xilinx.com 91UG380 (v2.7) October 29, 2014eFUSEBitstream Encryption and Internal Configuration Access Port
92 www.xilinx.com Spartan-6 FPGA Configuration User GuideUG380 (v2.7) October 29, 2014Chapter 5: Configuration DetailseFUSE RegistersA Spartan-6 FPGA
Spartan-6 FPGA Configuration User Guide www.xilinx.com 93UG380 (v2.7) October 29, 2014eFUSEIf CNTL[17] is NOT programmed:• Encryption can be enabled o
94 www.xilinx.com Spartan-6 FPGA Configuration User GuideUG380 (v2.7) October 29, 2014Chapter 5: Configuration DetailsJTAG InstructionseFUSE registers
Spartan-6 FPGA Configuration User Guide www.xilinx.com 95UG380 (v2.7) October 29, 2014Configuration Memory FramesConfiguration Memory FramesSpartan-6
96 www.xilinx.com Spartan-6 FPGA Configuration User GuideUG380 (v2.7) October 29, 2014Chapter 5: Configuration DetailsConfiguration PacketsAll Spartan
Spartan-6 FPGA Configuration User Guide www.xilinx.com 97UG380 (v2.7) October 29, 2014Configuration PacketsThe Type 2 word count follows the Type 2 pa
98 www.xilinx.com Spartan-6 FPGA Configuration User GuideUG380 (v2.7) October 29, 2014Chapter 5: Configuration DetailsCRC RegisterThe Cyclic Redundanc
Spartan-6 FPGA Configuration User Guide www.xilinx.com 99UG380 (v2.7) October 29, 2014Configuration PacketsFAR_MAJ Register Frame Address Register set
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